Introduction

The increasing demand for artificial intelligence (AI) at the edge has driven significant research into energy-efficient hardware accelerators. SRAM-based Compute-in-Memory (CIM) has emerged as a promising solution, offering the potential to perform computations directly within memory arrays, thereby reducing data movement and improving energy efficiency. This mini-review examines recent advancements in SRAM-based CIM architectures over the past five years, focusing on innovations in macro design, bitcell architectures, and precision scaling for AI edge applications.

Advancements in SRAM-Based CIM Macro Design

A significant area of research focuses on developing novel SRAM-based CIM macros to enhance performance and energy efficiency. Meng-Fan Chang's research group at National Yang Ming Chiao Tung University has been actively involved in this area, exploring various 6T-SRAM CIM macros for AI edge chips. In 2020, they presented a 64Kb 6T SRAM CIM macro with 8b MAC operation for AI edge chips (Xin Si et al., 2020). They also explored inference-training two-way transpose multibit 6T SRAM CIM macros (Jian-Wei Su et al., 2020) and macros with 8b precision (Jian-Wei Su et al., 2020). Their work extends to local computing cell designs (Xin Si et al., 2020) and configurable CIM unit-macros for CNN-based AI edge processors (Yen-Cheng Chiu et al., 2020). This research group also published a review paper in 2020 and 2021 outlining the challenges and trends of SRAM-based CIM for AI edge devices (Chuan-Jia Jhang et al., 2020, IEEE Transactions on Circuits and Systems I Regular Papers). More recently, they have focused on time-domain CIM macros (Ping-Chun Wu et al., 2021, Ping-Chun Wu et al., 2022) and floating-point CIM macros (Ping-Chun Wu et al., 2023).

Jonathan Chang's group at National Tsing Hua University has also made significant contributions, presenting a 7nm CIM SRAM macro achieving 351 TOPS/W and 372.4 GOPS (Qing Dong et al., 2020, Mahmut E. Sinangil et al., 2020, IEEE Journal of Solid-State Circuits). Their work has progressed to developing all-digital full-precision SRAM-based CIM with configurable bit-width (Chia-Fu Lee et al., 2022) and high-performance macros supporting bit-width flexibility and simultaneous MAC and weight update (H. Mori et al., 2023).

These advancements highlight a trend towards higher energy efficiency (TOPS/W), increased computational throughput (GOPS/TFLOPS), and greater flexibility in bit-width configuration to support diverse AI workloads.

Innovations in SRAM Bitcell Architectures for CIM

Another crucial area of development is the design of novel SRAM bitcell architectures optimized for CIM operations. Mingoo Seok's group at Columbia University has explored various approaches, including XNOR-SRAM for binary/ternary deep neural networks (Shihui Yin et al., 2020, IEEE Journal of Solid-State Circuits) and C3SRAM based on a robust capacitive coupling computing mechanism (Zhewei Jiang et al., 2020, IEEE Journal of Solid-State Circuits). Their research extends to capacitor-based in-memory computing SRAM macros (Bo Zhang et al., 2022) and digital in-memory computing macros based on approximate arithmetic hardware (Dewei Wang et al., 2022).

Bongjin Kim's group at the University of Michigan has focused on current-based SRAM CIM macros (Chengshuo Yu et al., 2020) and reconfigurable digital bit-serial CIM macros (Hyunjoon Kim et al., 2020, IEEE Journal of Solid-State Circuits, Hyunjoon Kim et al., 2021, IEEE Journal of Solid-State Circuits, Hyunjoon Kim et al., 2023, IEEE Transactions on Circuits and Systems I Regular Papers). They have also explored 8T SRAM CIM macros with column ADCs (Chengshuo Yu et al., 2022, IEEE Journal of Solid-State Circuits).

Kaiyuan Yang's group at the Hong Kong University of Science and Technology has investigated charge-domain in-memory computing 6T-SRAM for CNN inference (Zhiyu Chen et al., 2020, IEEE Journal of Solid-State Circuits, Zhiyu Chen et al., 2021, IEEE Journal of Solid-State Circuits). Ru Huang's group at Peking University has also explored charge-domain SRAM CIM macros (Bonan Yan et al., 2021, Bonan Yan et al., 2022, Jiahao Song et al., 2023, IEEE Transactions on Circuits and Systems I Regular Papers, Peiyu Chen et al., 2023).

These efforts demonstrate a diverse range of bitcell designs aimed at optimizing CIM performance, including XNOR-based, capacitive coupling-based, current-based, and charge-domain approaches.

Addressing Reliability and Low-Power Concerns

Beyond performance, reliability and power consumption are critical considerations for SRAM design, especially in harsh environments or low-power applications. Aminul Islam's group at the University of Louisiana at Lafayette has focused on soft-error resilient SRAM designs for space applications (Soumitra Pal et al., 2021, IEEE Transactions on Electron Devices, Soumitra Pal et al., 2021, IEEE Transactions on Circuits and Systems I Regular Papers). Chi-Ying Tsui's group at the Hong Kong University of Science and Technology has also worked on soft-error-aware SRAM designs (Soumitra Pal et al., 2022, IEEE Transactions on Circuits and Systems I Regular Papers).

Morteza Gholipour's group at Shahrood University of Technology has explored low-power SRAM cell designs, including 10T SRAM cells with expanded static noise margins (Erfan Abbasian et al., 2021, IEEE Transactions on Circuits and Systems I Regular Papers, Erfan Abbasian et al., 2022, IEEE Transactions on Circuits and Systems I Regular Papers), Schmitt-trigger-based 7T SRAM cells (Erfan Abbasian et al., 2021, AEU - International Journal of Electronics and Communications), and ultra-low-power 10T SRAM designs (Erfan Abbasian et al., 2022, Microelectronics Journal). Rohit Lorenzo's group at the University of Petroleum and Energy Studies has also focused on low-leakage SRAM cell designs (Rohit Lorenzo et al., 2022, International Journal of Circuit Theory and Applications).

These efforts highlight the importance of addressing reliability and power consumption challenges in SRAM design, particularly for applications in harsh environments and low-power devices.

Conclusion

The past five years have witnessed significant advancements in SRAM-based CIM architectures, driven by the growing demand for energy-efficient AI edge computing. Research has focused on developing novel macro designs, optimizing bitcell architectures for CIM operations, and addressing reliability and low-power concerns. These advancements pave the way for more efficient and powerful AI edge devices, enabling a wide range of applications in areas such as IoT, autonomous vehicles, and healthcare. Future research directions include exploring new materials and device technologies, developing more sophisticated CIM algorithms, and addressing the challenges of security and privacy in edge computing environments.

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